The C and C++ Include Header Files

/usr/include/drm/msm_drm.h


$ cat -n /usr/include/drm/msm_drm.h

     1	/*
     2	 * Copyright (C) 2013 Red Hat
     3	 * Author: Rob Clark <robdclark@gmail.com>
     4	 *
     5	 * Permission is hereby granted, free of charge, to any person obtaining a
     6	 * copy of this software and associated documentation files (the "Software"),
     7	 * to deal in the Software without restriction, including without limitation
     8	 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     9	 * and/or sell copies of the Software, and to permit persons to whom the
    10	 * Software is furnished to do so, subject to the following conditions:
    11	 *
    12	 * The above copyright notice and this permission notice (including the next
    13	 * paragraph) shall be included in all copies or substantial portions of the
    14	 * Software.
    15	 *
    16	 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    17	 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    18	 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
    19	 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    20	 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    21	 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
    22	 * SOFTWARE.
    23	 */
    24	
    25	#ifndef __MSM_DRM_H__
    26	#define __MSM_DRM_H__
    27	
    28	#include "drm.h"
    29	
    30	#if defined(__cplusplus)
    31	extern "C" {
    32	#endif
    33	
    34	/* Please note that modifications to all structs defined here are
    35	 * subject to backwards-compatibility constraints:
    36	 *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
    37	 *     user/kernel compatibility
    38	 *  2) Keep fields aligned to their size
    39	 *  3) Because of how drm_ioctl() works, we can add new fields at
    40	 *     the end of an ioctl if some care is taken: drm_ioctl() will
    41	 *     zero out the new fields at the tail of the ioctl, so a zero
    42	 *     value should have a backwards compatible meaning.  And for
    43	 *     output params, userspace won't see the newly added output
    44	 *     fields.. so that has to be somehow ok.
    45	 */
    46	
    47	#define MSM_PIPE_NONE        0x00
    48	#define MSM_PIPE_2D0         0x01
    49	#define MSM_PIPE_2D1         0x02
    50	#define MSM_PIPE_3D0         0x10
    51	
    52	/* The pipe-id just uses the lower bits, so can be OR'd with flags in
    53	 * the upper 16 bits (which could be extended further, if needed, maybe
    54	 * we extend/overload the pipe-id some day to deal with multiple rings,
    55	 * but even then I don't think we need the full lower 16 bits).
    56	 */
    57	#define MSM_PIPE_ID_MASK     0xffff
    58	#define MSM_PIPE_ID(x)       ((x) & MSM_PIPE_ID_MASK)
    59	#define MSM_PIPE_FLAGS(x)    ((x) & ~MSM_PIPE_ID_MASK)
    60	
    61	/* timeouts are specified in clock-monotonic absolute times (to simplify
    62	 * restarting interrupted ioctls).  The following struct is logically the
    63	 * same as 'struct timespec' but 32/64b ABI safe.
    64	 */
    65	struct drm_msm_timespec {
    66		__s64 tv_sec;          /* seconds */
    67		__s64 tv_nsec;         /* nanoseconds */
    68	};
    69	
    70	/* Below "RO" indicates a read-only param, "WO" indicates write-only, and
    71	 * "RW" indicates a param that can be both read (GET_PARAM) and written
    72	 * (SET_PARAM)
    73	 */
    74	#define MSM_PARAM_GPU_ID     0x01  /* RO */
    75	#define MSM_PARAM_GMEM_SIZE  0x02  /* RO */
    76	#define MSM_PARAM_CHIP_ID    0x03  /* RO */
    77	#define MSM_PARAM_MAX_FREQ   0x04  /* RO */
    78	#define MSM_PARAM_TIMESTAMP  0x05  /* RO */
    79	#define MSM_PARAM_GMEM_BASE  0x06  /* RO */
    80	#define MSM_PARAM_PRIORITIES 0x07  /* RO: The # of priority levels */
    81	#define MSM_PARAM_PP_PGTABLE 0x08  /* RO: Deprecated, always returns zero */
    82	#define MSM_PARAM_FAULTS     0x09  /* RO */
    83	#define MSM_PARAM_SUSPENDS   0x0a  /* RO */
    84	#define MSM_PARAM_SYSPROF    0x0b  /* WO: 1 preserves perfcntrs, 2 also disables suspend */
    85	#define MSM_PARAM_COMM       0x0c  /* WO: override for task->comm */
    86	#define MSM_PARAM_CMDLINE    0x0d  /* WO: override for task cmdline */
    87	#define MSM_PARAM_VA_START   0x0e  /* RO: start of valid GPU iova range */
    88	#define MSM_PARAM_VA_SIZE    0x0f  /* RO: size of valid GPU iova range (bytes) */
    89	#define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */
    90	
    91	/* For backwards compat.  The original support for preemption was based on
    92	 * a single ring per priority level so # of priority levels equals the #
    93	 * of rings.  With drm/scheduler providing additional levels of priority,
    94	 * the number of priorities is greater than the # of rings.  The param is
    95	 * renamed to better reflect this.
    96	 */
    97	#define MSM_PARAM_NR_RINGS   MSM_PARAM_PRIORITIES
    98	
    99	struct drm_msm_param {
   100		__u32 pipe;           /* in, MSM_PIPE_x */
   101		__u32 param;          /* in, MSM_PARAM_x */
   102		__u64 value;          /* out (get_param) or in (set_param) */
   103		__u32 len;            /* zero for non-pointer params */
   104		__u32 pad;            /* must be zero */
   105	};
   106	
   107	/*
   108	 * GEM buffers:
   109	 */
   110	
   111	#define MSM_BO_SCANOUT       0x00000001     /* scanout capable */
   112	#define MSM_BO_GPU_READONLY  0x00000002
   113	#define MSM_BO_CACHE_MASK    0x000f0000
   114	/* cache modes */
   115	#define MSM_BO_CACHED        0x00010000
   116	#define MSM_BO_WC            0x00020000
   117	#define MSM_BO_UNCACHED      0x00040000 /* deprecated, use MSM_BO_WC */
   118	#define MSM_BO_CACHED_COHERENT 0x080000
   119	
   120	#define MSM_BO_FLAGS         (MSM_BO_SCANOUT | \
   121	                              MSM_BO_GPU_READONLY | \
   122	                              MSM_BO_CACHE_MASK)
   123	
   124	struct drm_msm_gem_new {
   125		__u64 size;           /* in */
   126		__u32 flags;          /* in, mask of MSM_BO_x */
   127		__u32 handle;         /* out */
   128	};
   129	
   130	/* Get or set GEM buffer info.  The requested value can be passed
   131	 * directly in 'value', or for data larger than 64b 'value' is a
   132	 * pointer to userspace buffer, with 'len' specifying the number of
   133	 * bytes copied into that buffer.  For info returned by pointer,
   134	 * calling the GEM_INFO ioctl with null 'value' will return the
   135	 * required buffer size in 'len'
   136	 */
   137	#define MSM_INFO_GET_OFFSET	0x00   /* get mmap() offset, returned by value */
   138	#define MSM_INFO_GET_IOVA	0x01   /* get iova, returned by value */
   139	#define MSM_INFO_SET_NAME	0x02   /* set the debug name (by pointer) */
   140	#define MSM_INFO_GET_NAME	0x03   /* get debug name, returned by pointer */
   141	#define MSM_INFO_SET_IOVA	0x04   /* set the iova, passed by value */
   142	#define MSM_INFO_GET_FLAGS	0x05   /* get the MSM_BO_x flags */
   143	#define MSM_INFO_SET_METADATA	0x06   /* set userspace metadata */
   144	#define MSM_INFO_GET_METADATA	0x07   /* get userspace metadata */
   145	
   146	struct drm_msm_gem_info {
   147		__u32 handle;         /* in */
   148		__u32 info;           /* in - one of MSM_INFO_* */
   149		__u64 value;          /* in or out */
   150		__u32 len;            /* in or out */
   151		__u32 pad;
   152	};
   153	
   154	#define MSM_PREP_READ        0x01
   155	#define MSM_PREP_WRITE       0x02
   156	#define MSM_PREP_NOSYNC      0x04
   157	#define MSM_PREP_BOOST       0x08
   158	
   159	#define MSM_PREP_FLAGS       (MSM_PREP_READ | \
   160				      MSM_PREP_WRITE | \
   161				      MSM_PREP_NOSYNC | \
   162				      MSM_PREP_BOOST | \
   163				      0)
   164	
   165	struct drm_msm_gem_cpu_prep {
   166		__u32 handle;         /* in */
   167		__u32 op;             /* in, mask of MSM_PREP_x */
   168		struct drm_msm_timespec timeout;   /* in */
   169	};
   170	
   171	struct drm_msm_gem_cpu_fini {
   172		__u32 handle;         /* in */
   173	};
   174	
   175	/*
   176	 * Cmdstream Submission:
   177	 */
   178	
   179	/* The value written into the cmdstream is logically:
   180	 *
   181	 *   ((relocbuf->gpuaddr + reloc_offset) << shift) | or
   182	 *
   183	 * When we have GPU's w/ >32bit ptrs, it should be possible to deal
   184	 * with this by emit'ing two reloc entries with appropriate shift
   185	 * values.  Or a new MSM_SUBMIT_CMD_x type would also be an option.
   186	 *
   187	 * NOTE that reloc's must be sorted by order of increasing submit_offset,
   188	 * otherwise EINVAL.
   189	 */
   190	struct drm_msm_gem_submit_reloc {
   191		__u32 submit_offset;  /* in, offset from submit_bo */
   192	#ifdef __cplusplus
   193		__u32 _or;            /* in, value OR'd with result */
   194	#else
   195		__u32 or;             /* in, value OR'd with result */
   196	#endif
   197		__s32 shift;          /* in, amount of left shift (can be negative) */
   198		__u32 reloc_idx;      /* in, index of reloc_bo buffer */
   199		__u64 reloc_offset;   /* in, offset from start of reloc_bo */
   200	};
   201	
   202	/* submit-types:
   203	 *   BUF - this cmd buffer is executed normally.
   204	 *   IB_TARGET_BUF - this cmd buffer is an IB target.  Reloc's are
   205	 *      processed normally, but the kernel does not setup an IB to
   206	 *      this buffer in the first-level ringbuffer
   207	 *   CTX_RESTORE_BUF - only executed if there has been a GPU context
   208	 *      switch since the last SUBMIT ioctl
   209	 */
   210	#define MSM_SUBMIT_CMD_BUF             0x0001
   211	#define MSM_SUBMIT_CMD_IB_TARGET_BUF   0x0002
   212	#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
   213	struct drm_msm_gem_submit_cmd {
   214		__u32 type;           /* in, one of MSM_SUBMIT_CMD_x */
   215		__u32 submit_idx;     /* in, index of submit_bo cmdstream buffer */
   216		__u32 submit_offset;  /* in, offset into submit_bo */
   217		__u32 size;           /* in, cmdstream size */
   218		__u32 pad;
   219		__u32 nr_relocs;      /* in, number of submit_reloc's */
   220		__u64 relocs;         /* in, ptr to array of submit_reloc's */
   221	};
   222	
   223	/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
   224	 * cmdstream buffer(s) themselves or reloc entries) has one (and only
   225	 * one) entry in the submit->bos[] table.
   226	 *
   227	 * As a optimization, the current buffer (gpu virtual address) can be
   228	 * passed back through the 'presumed' field.  If on a subsequent reloc,
   229	 * userspace passes back a 'presumed' address that is still valid,
   230	 * then patching the cmdstream for this entry is skipped.  This can
   231	 * avoid kernel needing to map/access the cmdstream bo in the common
   232	 * case.
   233	 */
   234	#define MSM_SUBMIT_BO_READ             0x0001
   235	#define MSM_SUBMIT_BO_WRITE            0x0002
   236	#define MSM_SUBMIT_BO_DUMP             0x0004
   237	#define MSM_SUBMIT_BO_NO_IMPLICIT      0x0008
   238	
   239	#define MSM_SUBMIT_BO_FLAGS            (MSM_SUBMIT_BO_READ | \
   240						MSM_SUBMIT_BO_WRITE | \
   241						MSM_SUBMIT_BO_DUMP | \
   242						MSM_SUBMIT_BO_NO_IMPLICIT)
   243	
   244	struct drm_msm_gem_submit_bo {
   245		__u32 flags;          /* in, mask of MSM_SUBMIT_BO_x */
   246		__u32 handle;         /* in, GEM handle */
   247		__u64 presumed;       /* in/out, presumed buffer address */
   248	};
   249	
   250	/* Valid submit ioctl flags: */
   251	#define MSM_SUBMIT_NO_IMPLICIT   0x80000000 /* disable implicit sync */
   252	#define MSM_SUBMIT_FENCE_FD_IN   0x40000000 /* enable input fence_fd */
   253	#define MSM_SUBMIT_FENCE_FD_OUT  0x20000000 /* enable output fence_fd */
   254	#define MSM_SUBMIT_SUDO          0x10000000 /* run submitted cmds from RB */
   255	#define MSM_SUBMIT_SYNCOBJ_IN    0x08000000 /* enable input syncobj */
   256	#define MSM_SUBMIT_SYNCOBJ_OUT   0x04000000 /* enable output syncobj */
   257	#define MSM_SUBMIT_FENCE_SN_IN   0x02000000 /* userspace passes in seqno fence */
   258	#define MSM_SUBMIT_FLAGS                ( \
   259			MSM_SUBMIT_NO_IMPLICIT   | \
   260			MSM_SUBMIT_FENCE_FD_IN   | \
   261			MSM_SUBMIT_FENCE_FD_OUT  | \
   262			MSM_SUBMIT_SUDO          | \
   263			MSM_SUBMIT_SYNCOBJ_IN    | \
   264			MSM_SUBMIT_SYNCOBJ_OUT   | \
   265			MSM_SUBMIT_FENCE_SN_IN   | \
   266			0)
   267	
   268	#define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
   269	#define MSM_SUBMIT_SYNCOBJ_FLAGS        ( \
   270			MSM_SUBMIT_SYNCOBJ_RESET | \
   271			0)
   272	
   273	struct drm_msm_gem_submit_syncobj {
   274		__u32 handle;     /* in, syncobj handle. */
   275		__u32 flags;      /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */
   276		__u64 point;      /* in, timepoint for timeline syncobjs. */
   277	};
   278	
   279	/* Each cmdstream submit consists of a table of buffers involved, and
   280	 * one or more cmdstream buffers.  This allows for conditional execution
   281	 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
   282	 */
   283	struct drm_msm_gem_submit {
   284		__u32 flags;          /* MSM_PIPE_x | MSM_SUBMIT_x */
   285		__u32 fence;          /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */
   286		__u32 nr_bos;         /* in, number of submit_bo's */
   287		__u32 nr_cmds;        /* in, number of submit_cmd's */
   288		__u64 bos;            /* in, ptr to array of submit_bo's */
   289		__u64 cmds;           /* in, ptr to array of submit_cmd's */
   290		__s32 fence_fd;       /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
   291		__u32 queueid;        /* in, submitqueue id */
   292		__u64 in_syncobjs;    /* in, ptr to array of drm_msm_gem_submit_syncobj */
   293		__u64 out_syncobjs;   /* in, ptr to array of drm_msm_gem_submit_syncobj */
   294		__u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
   295		__u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
   296		__u32 syncobj_stride; /* in, stride of syncobj arrays. */
   297		__u32 pad;            /*in, reserved for future use, always 0. */
   298	
   299	};
   300	
   301	#define MSM_WAIT_FENCE_BOOST	0x00000001
   302	#define MSM_WAIT_FENCE_FLAGS	( \
   303			MSM_WAIT_FENCE_BOOST | \
   304			0)
   305	
   306	/* The normal way to synchronize with the GPU is just to CPU_PREP on
   307	 * a buffer if you need to access it from the CPU (other cmdstream
   308	 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
   309	 * handle the required synchronization under the hood).  This ioctl
   310	 * mainly just exists as a way to implement the gallium pipe_fence
   311	 * APIs without requiring a dummy bo to synchronize on.
   312	 */
   313	struct drm_msm_wait_fence {
   314		__u32 fence;          /* in */
   315		__u32 flags;          /* in, bitmask of MSM_WAIT_FENCE_x */
   316		struct drm_msm_timespec timeout;   /* in */
   317		__u32 queueid;         /* in, submitqueue id */
   318	};
   319	
   320	/* madvise provides a way to tell the kernel in case a buffers contents
   321	 * can be discarded under memory pressure, which is useful for userspace
   322	 * bo cache where we want to optimistically hold on to buffer allocate
   323	 * and potential mmap, but allow the pages to be discarded under memory
   324	 * pressure.
   325	 *
   326	 * Typical usage would involve madvise(DONTNEED) when buffer enters BO
   327	 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
   328	 * In the WILLNEED case, 'retained' indicates to userspace whether the
   329	 * backing pages still exist.
   330	 */
   331	#define MSM_MADV_WILLNEED 0       /* backing pages are needed, status returned in 'retained' */
   332	#define MSM_MADV_DONTNEED 1       /* backing pages not needed */
   333	#define __MSM_MADV_PURGED 2       /* internal state */
   334	
   335	struct drm_msm_gem_madvise {
   336		__u32 handle;         /* in, GEM handle */
   337		__u32 madv;           /* in, MSM_MADV_x */
   338		__u32 retained;       /* out, whether backing store still exists */
   339	};
   340	
   341	/*
   342	 * Draw queues allow the user to set specific submission parameter. Command
   343	 * submissions specify a specific submitqueue to use.  ID 0 is reserved for
   344	 * backwards compatibility as a "default" submitqueue
   345	 */
   346	
   347	#define MSM_SUBMITQUEUE_FLAGS (0)
   348	
   349	/*
   350	 * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
   351	 * a lower numeric value is higher priority.
   352	 */
   353	struct drm_msm_submitqueue {
   354		__u32 flags;   /* in, MSM_SUBMITQUEUE_x */
   355		__u32 prio;    /* in, Priority level */
   356		__u32 id;      /* out, identifier */
   357	};
   358	
   359	#define MSM_SUBMITQUEUE_PARAM_FAULTS   0
   360	
   361	struct drm_msm_submitqueue_query {
   362		__u64 data;
   363		__u32 id;
   364		__u32 param;
   365		__u32 len;
   366		__u32 pad;
   367	};
   368	
   369	#define DRM_MSM_GET_PARAM              0x00
   370	#define DRM_MSM_SET_PARAM              0x01
   371	#define DRM_MSM_GEM_NEW                0x02
   372	#define DRM_MSM_GEM_INFO               0x03
   373	#define DRM_MSM_GEM_CPU_PREP           0x04
   374	#define DRM_MSM_GEM_CPU_FINI           0x05
   375	#define DRM_MSM_GEM_SUBMIT             0x06
   376	#define DRM_MSM_WAIT_FENCE             0x07
   377	#define DRM_MSM_GEM_MADVISE            0x08
   378	/* placeholder:
   379	#define DRM_MSM_GEM_SVM_NEW            0x09
   380	 */
   381	#define DRM_MSM_SUBMITQUEUE_NEW        0x0A
   382	#define DRM_MSM_SUBMITQUEUE_CLOSE      0x0B
   383	#define DRM_MSM_SUBMITQUEUE_QUERY      0x0C
   384	
   385	#define DRM_IOCTL_MSM_GET_PARAM        DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
   386	#define DRM_IOCTL_MSM_SET_PARAM        DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)
   387	#define DRM_IOCTL_MSM_GEM_NEW          DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
   388	#define DRM_IOCTL_MSM_GEM_INFO         DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
   389	#define DRM_IOCTL_MSM_GEM_CPU_PREP     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
   390	#define DRM_IOCTL_MSM_GEM_CPU_FINI     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
   391	#define DRM_IOCTL_MSM_GEM_SUBMIT       DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
   392	#define DRM_IOCTL_MSM_WAIT_FENCE       DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
   393	#define DRM_IOCTL_MSM_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
   394	#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW    DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
   395	#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE  DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
   396	#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY  DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
   397	
   398	#if defined(__cplusplus)
   399	}
   400	#endif
   401	
   402	#endif /* __MSM_DRM_H__ */